The present invention relates generally to the field of processors and in particular to a method of bus arbitration that considers data transfer direction and bus channel bandwidth consumption.
Portable electronic devices continue to increase in sophistication and computing power, providing ever-increasing functionality to users. Modern portable electronic devices may include wireless data and voice communications; photographic and video capture and playback; position determination and geographic routing; game-playing with sophisticated graphics; high-fidelity audio reception and playback; and the like. In the near future, portable electronic devices are anticipated to support ubiquitous ad hoc data communications (e.g., IEEE 802.11, Bluetooth, and the like), virtual reality user interfaces, and many other advances. In many cases, such diverse functionality is implemented with dedicated processing circuits, in addition to one or more main processors. For example, a graphics coprocessor, MPEG video en/decoder, GPS receiver processor and/or other dedicated processors may reside in a portable electronic device, and may share system resources, such as memory, user interface elements, and the like.
The efficient transfer of data between functional units is a fundamental operation of any digital system, including portable electronic devices. Transferring a program from disk to memory to a processor; sending data from a graphics engine to a frame buffer to a video display circuit; and sending input from a keypad, mouse or touch screen to a processor are all common examples of data transfer within a computing system.
FIG. 1 depicts a simplified diagram of a well-known system bus architecture, indicated generally by the numeral 10. A system bus 12 interconnects system units. The system bus 12 may comprise address, data and control channels, and may perform bidirectional (e.g., read and write) data transfers. Master devices, such as the CPU 14 or a DMA engine 16, initiate data transfers across one or more channels of the bus 12—referred to herein as bus transactions—to or from slave devices, such as memory 18 and input/output circuits 20. When two or more independent masters 14, 16 are connected to the bus 12, their access to the bus is controlled by an arbiter 22.
As known in the art, one or more master devices 14, 16 assert a bus request to the arbiter 22. The arbiter 22 monitors activity on the bus 12, and when the bus 12 becomes available, sends a bus grant to one of the requesting master devices 14, 16. The granted master device 14, 16 may then initiate transactions across one or more channels of the bus 12, such as read or write cycles directed to one or more slave devices 18, 20.
Numerous bus arbitration algorithms are known in the art. Copending U.S. patent application Ser. No. 10/833,716, filed Apr. 27, 2004, assigned to the assignee of the present invention and incorporated by reference herein in its entirety, discloses a bus arbitration scheme in which each master device is initially assigned a programmable weighting. As each master device is granted access to the bus, its weighting register is decremented, effectively lowering the request priority of that master device relative to the other master devices with pending requests. The arbiter implements a weighted round-robin arbitration algorithm, wherein master devices with higher weightings have priority over master devices with a lower weighting, with a round-robin selection among master devices having the same weighting. Once all master devices have decremented their weighting registers to zero, a fair round-robin arbitration is implemented for the duration of a weighting interval, at the expiration of which all master devices are re-assigned their initial programmable weighting.
In one embodiment, two or more tiers of master devices may be defined. The programmable weighting of higher-tiered master devices may be updated at a frequency higher than that of lower-tiered master devices. Thus, as the master devices' weightings are decremented as each master device is granted a bus transaction cycle during the weighting interval, the higher-tiered master devices may be reset to their initial weightings on a more frequent basis, effectively giving the higher-tier master devices an overall higher priority.
This arbitration scheme is effective for sharing bus resources among multiple master devices in an equitable manner; master devices that access the bus only infrequently retain a higher priority, and devices that perform a large number of bus transactions quickly deplete their relative priority.
However, the number of bus transactions performed by a master device is only a rough approximation of that master device's consumption of available bus bandwidth. For example, a read burst comprising sixteen data transfer cycles, or “beats” (i.e., 128 bytes for a 64-bit data bus) consumes far greater bus bandwidth than does a byte read that requires only one bus beat. However, the above-described arbitration scheme would decrement a master device's weighting register the same amount in either case.
Additionally, modern high-performance busses may comprise independent read and write bus channels, with master devices utilizing the read and write bus channels in varying amounts. As the above-described arbitration algorithm does not take into account which channel a master device is utilizing, its arbitration weighting scheme does not accurately reflect a master device's actual bus bandwidth consumption.